The present invention relates to a semiconductor memory, and more particularly, to a semiconductor memory having a block write function whereby data can be written into a plurality of column addresses thereof simultaneously and selectively.
In an ordinary semiconductor memory, data are written by one access at one particular column address designated by column address data supplied. Another type of semiconductor memory has a so called block write function, whereby data can be written into a plurality of column addresses, selected according to the higher bit sequence of the column address data by ignoring a certain number of lower bits of the column address data corresponding to the number of columns to be written simultaneously. For example, in an eight column block, write operation, that is, when data are to be written in eight succeeding columns simultaneously, the lower three bits of the column address data are ignored.
In semiconductor memories having the block write function, a column mask function is generally also provided, whereby permission or prohibition of data write is controlled for each of the selected columns according to column mask signals. In this block write mode, the column mask signals take charge of individual column selection among the selected sequence of columns, in place of the ignored lower bits of the column address data.
There are also semiconductor memories that use a column redundancy address for each of their memory cell arrays. When column address data designate a defective digit line, where any defective memory cell is found in the production process, it is discriminated by a redundancy discrimination circuit and the defective column address is replaced by the column redundancy address, in a normal write mode or read-out mode.
However, in the block write mode, a redundancy discrimination circuit must also discriminate whether the defective digit line is designated or not, according to the column mask signals as well as the higher bit sequence of the column address data.
Generally, a redundancy discrimination circuit comprises a certain number of fuses together with a logic circuit. The fuses, which are to be cut by a laser beam, need comparatively wide spaces of the memory chip. Therefore, a decrease of the number in fuses for a column redundancy discrimination circuit, provided for each memory cell array, is important for reducing the chip size of a semiconductor memory.
FIG. 3 is a circuit diagram illustrating an example of a column redundancy discrimination circuit in a prior art a semiconductor memory, wherein an eight column block write is performed. The array configuration of this semiconductor memory is illustrated in FIG. 4.
First, the configuration of the column redundancy discrimination circuit shown in FIG. 3 will be described.
The column redundancy discrimination circuit of FIG. 3 has a normal redundancy discrimination circuit and a block write redundancy discrimination circuit.
The normal redundancy discrimination circuit comprises:
seven pairs of fuses H0T, H0N to H6T, H6N, where an end of each fuse is connected to a node A for outputting a column redundancy discrimination signal RD; PA1 seven pairs of transfer gates Tr0T, Tr0N to Tr6T, Tr6N, each thereof connected between ground and the other end of a corresponding fuse of the seven pairs of fuses H0T, H0N to H6T, H6N; and PA1 a transfer gate Tr21, controlled by a pre-charge signal PR and provided between a power supply and the node A. PA1 eight fuses H30 to H37, an end of each thereof connected to a node B, PA1 eight transfer gates Tr30 to Tr37, each thereof connected between ground and the other end of each of the eight corresponding fuses H30 to H37, PA1 a transfer gate Tr23, controlled by a pre-charge signal PR and provided between a power supply and the node B, PA1 a NOR gate N1 for outputting NOR logic of a block write control signal BW and logic of the node B, and PA1 a transfer gate Tr22 connected between the node A and ground and controlled by the output of the NOR gate N1. PA1 a first and a second memory cell arrays both driven by a common row decoder, where the LSB (Least Significant Bit) of the column address data corresponding to each of the memory cells of the first memory cell array is `0` and that of the second memory cell array `1`, PA1 a first and a second column decoders, wherein either the first or the second column decoders selects a memory cell corresponding to the column address data by decoding variable bits of the column address data other than the LSB in a normal write mode, and where each of the first and the second column decoders selects memory cells according to a logic that uses bits higher than the lower three bits of the column address data, according to half of eight column mask signals corresponding to logic of the second and a third lower bits, in a block write mode; and PA1 a first and a second column redundancy discrimination circuit, each controlling, respectively, the first and the second column decoders as the decoders replace a data write operation into a memory cell connected to a defective digit line by a data write operation into a corresponding memory cell connected to a redundant digit line, where the controlling includes watching logic of the variable bits in the normal write mode, and watching logic of the higher bits and the corresponding half of the eight column mask signals in the block write mode.
The block write redundancy discrimination circuit comprises:
Before the column redundancy discrimination, the node A and the node B are pre-charged at logic HIGH through the transfer gates Tr21 and Tr23 controlled by the pre-charge signal PR.
Operation of the column redundancy discrimination circuit of FIG. 3 will now be described.
When a defective column address is found in the memory cell array, either one of each of the seven pairs of fuses H0T, H0N to H6T, H6N is cut, according to the defective column address. When the defective column address is `1111000` in binary code, for example, fuses H0N, H1N and H2N corresponding to logic `0` of the lower three bits, and H3T, H4T, H5T and H6T, corresponding to logic `1` of the higher four bits of the defective column address, are cut.
In the normal write mode, the gates of each pair of the seven pairs of transfer gates Tr0T, Tr0N to Tr6T, Tr6N is supplied with one of the corresponding seven pairs of complementary column address signals Y0T, Y0N to Y6T, Y6N, each pair thereof representing the logic and inverted logic of each of the corresponding lower seven bits of the column address data.
Therefore, when logic the lower seven bits of the column address data is `1111000`, that is, when the logic of the complementary column address signals Y0N, Y1N, Y2N, Y3T, Y4T, Y5T and Y6T is HIGH and logic of the other complementary column address signals is LOW, corresponding the transfer gates Tr0N, Tr1N, Tr2N, Tr3T, Tr4T, Tr5T and Tr6T are in an ON state. However, where every corresponding fuse is cut, the node A remains at logic HIGH, which allows the replacement by the column redundancy address. On the contrary, when the logic of the lower seven bits of the column address is not `1111000`, at least one of the transfer gates Tr0T, Tr1T, Tr2T, Tr3N, Tr4N, Tr5N and Tr6N turns ON and the node A is grounded through at least one of the uncut fuses. When grounded, the node A outputs the redundancy discrimination signal RD at logic LOW, disabling the replacement by the column redundancy address.
On the other hand, for the column redundancy discrimination in the block write mode, one of the eight fuses H30 to H37, that corresponds to the defective digit line is left uncut, the others of the eight fuses H30 to H37 being cut. In the case where the defective column address is `1111000`, the first fuse H30, corresponding to logic `000` of the lower three bits of the defective column address, is left uncut.
In the block write mode, the complementary column address signals Y0T, Y0N to Y2T, Y2N, corresponding to the lower three bits of the column address data are suppressed, and in place thereof, each of eight column mask signals CM0 to CM7, logic HIGH thereof prohibiting a data-write to a corresponding digit line, is supplied to the gate of each of the eight corresponding transfer gates Tr30 to Tr37 of the block write redundancy discrimination circuit.
Therefore, when a logic LOW is supplied to the first transfer gate Tr30 connected to the first fuse H30 corresponding to the defective digit line, that is, when the column address corresponding to the defective digit line is not masked, the logic of the node B remains at a logic HIGH making the output of the NOR gate N1 a logic LOW, which maintains the transfer gate Tr22, in an OFF state. So, the logic of the node A is determined according to the logic of the higher four pairs of the complementary column address signals Y3T, Y3N to Y6T, Y6N, indicating a column block where the block write is to be performed and the column redundancy replacement is performed when the higher bits of the column address data coincide with those of the defective column address.
By comparison, when logic HIGH is supplied to the transfer gate Tr30 corresponding to the uncut fuse H30, that is, when block write to the defective digit line is masked, the node B is grounded, turning the transfer gate Tr22 ON, thereby prohibiting data write into the column redundancy address, so that the data previously written there are not revised.
Now configuration of memory cell arrays will be described referring to an example illustrated in FIG. 4.
In many semiconductor memories, row decoders are arranged so that they are divided over two or more memory cell arrays in order to reduce load for a particular word. In the example of FIG. 4, memory cells are divided into four memory cell arrays MCA41 to MCA44, according to the MSB (Most Significant Bit) of both the row address data and the column address data. Representing the logic of the MSB of the row address data by X8 and that of the column address data by Y7, a first row decoder RD1 is selected when X8=0, and a second row decoder RD2 is selected when X8=1. When Y7=0, a first and a third column decoders CD41 and CD43 are selected, while a second and a fourth decoders CD42 and CD44 are selected when Y7=1.
The same word lines of the memory cell arrays MCA41 and MCA42 or MCA43 and MCA44 are selected by the first row decoder RD1, or by the second row decoder RD2, according to the logic of the lower bits (X0 to X7) of the row address data and. The same digit lines of the memory cell arrays MCA41 and MCA43 or MCA42 and MCA44 are selected by the first and the third column decoders CD41 and CD43 or the second and the fourth column decoders CD42 and CD44, respectively, according to logic of the lower bits (Y0 to Y6) of the column address data.
In the normal write mode, two word lines WA of the memory cell arrays MCA41 and MCA42, or two other word lines WB of the memory cell arrays MCA43 and MCA44, are selected according to the row address data, as in the example of FIG. 4, and the memory cell arrays not having selected word lines are disabled. A digit line is then selected from digit lines in the two enabled memory cell arrays, specifying a designated memory cell.
Therefore, a column redundancy discrimination circuit (CRD41 to CRD44) must be provided for each of the memory cell arrays MCA41 to MCA44 thus arranged, for discriminating column address data designating each defective digit line.
Further, in the semiconductor memory having the block write function for as certain number of columns, each column redundancy discrimination circuit of the prior art must be provided with the same number of fuses as the number of columns to be selected simultaneously for the block write redundancy discrimination.
As previously described, miniaturization of fuses is difficult compared to other components of the semiconductor memory because they should be prepared to be cut separately by a laser beam after production of the semiconductor memory. Therefore, as the number of columns to be written with one block write and the number of memory cell arrays, increase, where memory cells of the same row address are divided, this results in a wider chip size of the semiconductor memory.
This is a problem presented by the prior art.